Sense amplifier and semiconductor memory device including the sense amplifier

ABSTRACT

A sense amplifier includes a bit line sense amplifier including a first transistor and a second transistor spaced apart from each other in a first direction, a second conductive line configured to electrically connect the first transistor to the second transistor and extending in the first direction and a local sense amplifier configured to at least partially overlap the second conductive line and disposed between the first transistor and the second transistor. The local sense amplifier includes an active region, a plurality of gate patterns at least partially extending in the first direction and disposed on the active region, a first contact disposed between the plurality of gate patterns and including a long side extending in the first direction and a short side extending in a second direction crossing the first direction and a first conductive line electrically connected to the first contact while overlapping the first contact in a plan view and including a first conductive region extending in the first direction.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35U.S.C. § 119 to Korean Patent Application No. 10-2020-0145306 filed onNov. 3, 2020 in the Korean Intellectual Property Office, the disclosureof which is incorporated by reference in its entirety herein.

1. TECHNICAL FIELD

The present disclosure relates to a sense amplifier and a semiconductormemory device including the sense amplifier.

2. DISCUSSION OF RELATED ART

With the development of the electronic industry, there is an everincreasing demand for electronic components that provide a large numberof functions, operate at high speeds, and a have a minimal size. Asemiconductor memory device is an example of one of these electroniccomponents. The semiconductor memory device includes a memory cell and aperipheral circuit to drive the memory cell. The area of the peripheralcircuit may be reduced to improve the integration density of thesemiconductor memory device.

The peripheral circuit includes a sense amplifier for amplifying avoltage difference between a bit line BL and a complementary bit lineBLB. As the integration density of the semiconductor memory deviceincreases, the area of the sense amplifier decreases. Thus, an area of acontact in the sense amplifier also decreases. However, the decrease inthe area of the contact causes a deterioration in the performance of thesemiconductor memory device.

SUMMARY

At least one embodiment of the present disclosure provide a senseamplifier whose operation performance is improved by increasing the areaof the contact in an active region.

At least one embodiment of the present disclosure also provides a senseamplifier in which the direction in which a gate pattern extends and thedirection in which a conductive line disposed on the gate patternextends coincide with each other.

According to an exemplary embodiment, a sense amplifier includes a bitline sense amplifier including a first transistor and a secondtransistor spaced apart from each other in a first direction, a secondconductive line configured to electrically connect the first transistorto the second transistor and extending in the first direction and alocal sense amplifier configured to at least partially overlap thesecond conductive line and disposed between the first transistor and thesecond transistor. The local sense amplifier includes an active region,a plurality of gate patterns at least partially extending in the firstdirection and disposed on the active region, a first contact disposedbetween the plurality of gate patterns and including a long sideextending in the first direction and a short side extending in a seconddirection crossing the first direction and a first conductive lineelectrically connected to the first contact while overlapping the firstcontact in a plan view and including a first conductive region extendingin the first direction.

According to an exemplary embodiment, a semiconductor memory deviceincludes a memory cell array including a plurality of memory cells, abit line sense amplifier including a first transistor and a secondtransistor configured to sense a potential difference between a bit lineand a complementary bit line during a sensing operation for theplurality of memory cells, an active region crossed by a secondconductive line electrically connecting the first transistor to thesecond transistor, a gate pattern at least partially overlapping thesecond conductive line in plan view and extending in a first directionin which the second conductive line extends, a first conductive lineextending in the first direction without at least partially overlappingthe gate pattern and the second conductive line and a first contactoverlapping the first conductive line and including a long sideextending in the first direction and a short side extending in a seconddirection crossing the first direction.

According to an exemplary embodiment, a semiconductor memory deviceincludes a memory cell array including a plurality of memory cellsconfigured to store data, a bit line sense amplifier including a firsttransistor and a second transistor configured to sense a potentialdifference between a first potential of a bit line and a secondpotential of a complementary bit line during a sensing operation for theplurality of memory cells, a local sense amplifier configured to receivethe first potential and the second potential from the bit line senseamplifier and provide data to a global input/output line. The localsense amplifier is disposed between the first transistor and the secondtransistor. The local sense amplifier includes an active region, aplurality of gate patterns disposed on the active region so as to atleast partially overlap a second conductive line electrically connectingthe first transistor to the second transistor, a first contact disposedbetween the plurality of gate patterns and including a long sideextending in a first direction in which the second conductive lineextends and a short side extending in a second direction crossing thefirst direction and a first conductive line electrically connected tothe first contact while overlapping the first contact in a plan view andincluding a first conductive region extending in the first direction.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will become more apparent by describing in detailexemplary embodiments thereof with reference to the attached drawings,in which:

FIG. 1 is a block diagram illustrating a computing system including asemiconductor memory device according to an exemplary embodiment of thepresent disclosure;

FIG. 2 is a block diagram illustrating a memory system including asemiconductor memory device according to an exemplary embodiment of thepresent disclosure;

FIG. 3 is a block diagram of a semiconductor memory device according toan exemplary embodiment of the present disclosure;

FIG. 4 shows an example of data output paths of the bit line senseamplifier and the local sense amplifier of FIG. 3 ;

FIG. 5 shows an example of the arrangement structure of the senseamplifier according to an embodiment of the present disclosure;

FIG. 6 is an exemplary circuit diagram illustrating a sense amplifier ofFIG. 5 ;

FIG. 7 is a layout diagram illustrating a sense amplifier according toan exemplary embodiment of the present disclosure;

FIG. 8 is a diagram for explaining a cross section taken along line A-A′of FIG. 7 ;

FIG. 9 is a diagram for explaining a cross section taken along line B-B′of FIG. 7 ;

FIG. 10 is a diagram for explaining a cross section taken along lineC-C′ of FIG. 7 ;

FIG. 11 is a layout diagram illustrating a sense amplifier according toan exemplary embodiment of the present disclosure;

FIG. 12 is a layout diagram illustrating a sense amplifier according toan exemplary embodiment of the present disclosure; and

FIG. 13 is a diagram for explaining the effect of a sense amplifieraccording to an exemplary embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Hereinafter, embodiments of the present disclosure will be describedwith reference to the accompanying drawings. In the followingdescription made with reference to FIGS. 1 to 13 , the same referencenumbers are used to refer to substantially the same components, and aredundant description of the corresponding components will be omitted.Like reference numbers refer to like elements throughout the variousdrawings.

FIG. 1 is a block diagram illustrating a computing system including asemiconductor memory device according to an exemplary embodiment of thepresent disclosure.

Referring to FIG. 1 , the computing system 1 includes a centralprocessing unit (CPU) 10, an input/output device (I/O) 20, an interfacedevice (INTERFACE) 30, a power supply device (POWER SUPPLY) 40, and amemory system 50.

The central processing unit 10, the input/output device 20, theinterface device 30, the power supply device 40, and the memory system50 may be connected to each other by a bus 60. The bus 60 corresponds toa path through which data is transferred.

The central processing unit 10 may include a single processor core(single core) or multiple processor cores (multi-core) to process data.For example, the central processing unit 10 may include the multi-coresuch as a dual-core, a quad-core, a hexa-core, or the like. The centralprocessing unit 10 may further include therein various hardware devices(e.g., IP core). The central processing unit 10 may include a cachememory disposed inside or outside the central processing unit 10.

The input/output device 20 may include one or more input devices such asa keypad and a touch screen, and/or one or more output devices such as aspeaker and a display device.

The interface device 30 may perform wireless communication or wiredcommunication with an external device. For example, the interface device30 may perform Ethernet communication, near field communication (NFC),radio frequency identification (RFID) communication, mobiletelecommunication, memory card communication, universal serial bus (USB)communication, or the like.

The memory system 50 may store data processed by the central processingunit 10 or may be driven as a working memory of the central processingunit 10. In an embodiment, the memory system 50 includes a memory device100 and a memory controller 200. The configurations of the memory device100 and the memory controller 200 may be substantially the same as thoseof the memory device 100 and the memory controller 200 to be describedwith reference to FIG. 2 , and a detailed description thereof will begiven later with reference to FIG. 2 .

The power supply device 40 may convert a power inputted from the outsideand provide it to the respective components 10 to 50. For example, thepower supply device 40 may convert power from an alternating current(AC) power source into direct current (DC) voltage for use by therespective components 10 to 50.

Although not shown, the computing system 1 may further include anonvolatile memory device. Examples of the nonvolatile memory device mayinclude a read only memory (ROM), a programmable ROM (PROM), anelectrically erasable programmable ROM (EEPROM), a flash memory, aphase-change RAM (PRAM), a resistive RAM (RRAM), a ferroelectric RAM(FRAM), and the like.

According to an embodiment, the computing system 1 may be any computingsystem such as a mobile phone, a smart phone, a personal digitalassistant (PDA), a portable multimedia player (PMP), a digital camera, amusic player, a portable game console, a navigation system, and thelike.

The steps of a method or an algorithm described in relation with theembodiments of the present disclosure may be directly implemented usinga hardware module, a software module, or a combination thereof executedby a processor such as the central processing unit 10. The softwaremodule may be permanently installed on a RAM memory, a flash memory, aROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk,a detachable disk, a CD-ROM, or any computer-readable storage mediumknown in the technical field of the present disclosure. A storage mediummay be connected to the processor, so that it is possible to readinformation from the processor and write information in the storagemedium. Alternatively, the storage medium may be integrally formed withthe processor. The processor and the storage medium may be permanentlymounted in an application specific integrated circuit (ASIC). The ASICmay be permanently mounted in a user terminal. Alternatively, theprocessor and the storage medium may be permanently mounted as separatecomponents in a user terminal.

FIG. 2 is a block diagram illustrating a memory system including asemiconductor memory device according to an exemplary embodiment of thepresent disclosure.

Referring to FIG. 2 , the memory system includes the semiconductormemory device (memory device) 100, and the memory controller 200.

The memory controller 200 is configured to control the semiconductormemory device 100. The memory controller 200 may access thesemiconductor memory device 100 in response to a request from a host.For example, the memory controller 200 may write data to thesemiconductor memory device 100 or read data from the semiconductormemory device 100 in response to the request.

Therefore, the memory controller 200 may provide a command CMD and anaddress ADDR to the semiconductor memory device 100 and exchange data DQwith the semiconductor memory device 100. The memory controller 200 maybe configured to drive firmware for controlling the semiconductor memorydevice 100.

The semiconductor memory device 100 is configured to store data. Forexample, the memory device 100 may be a DRAM such as a double data ratestatic DRAM (DDR SDRAM), a single data rate SDRAM (SDR SDRAM), a lowpower DDR SDRAM (LPDDR SDRAM), a low power SDR SDRAM (LPSDR SDRAM), anda direct Rambus DRAM (RDRAM), or any volatile memory device.

FIG. 3 is a block diagram of a semiconductor memory device according toan exemplary embodiment of the present disclosure.

Referring to FIG. 3 , the semiconductor memory device 100 includes amemory cell array 110, a row decoder 115 (e.g., a decoder circuit), abit line sense amplifier array 120, a column decoder 130 (e.g., adecoder circuit), an input/output (I/O) gate 140, a control logiccircuit 150, and a local sense amplifier (LSA) 160 or a LSA block.

The memory cell array 110 includes a plurality of memory cells 111arranged in a matrix shape of rows and columns. The memory cells 111 areconnected to word lines WL1 to WLn (n being a natural number) and bitlines BL1 to BLm (m being a natural number). The memory cells 111 may beclassified into normal memory cells and redundant memory cells. When thenormal memory cells are defective, the redundant memory cells are usedto repair the defective normal memory cells. Each of the bit lines BL1to BLm includes a bit line (e.g., a non-complementary bit line) and acomplementary bit line.

The memory cell 111 may be implemented as a volatile memory cell or anonvolatile memory cell. The volatile memory may be a dynamic randomaccess memory (DRAM), a static random access memory (SRAM), a thyristorRAM (TRAM), a zero capacitor RAM (Z-RAM), or a twin transistor RAM(TTRAM).

The nonvolatile memory may be an electrically erasable programmableread-only memory (EEPROM), a flash memory, a magnetic RAM (MRAM), aspin-transfer torque MRAM, a conductive bridging RAM (CBRAM), aferroelectric RAM (FeRAM), a phase change RAM (PRAM), a resistive RAM(RRAM), a nanotube RRAM, a polymer RAM (PoRAM), a nano floating gatememory (NFGM), a holographic memory, a molecular electronics memorydevice, or an insulator resistance change memory. The nonvolatile memorycell may store one or more bits.

The row decoder 115 decodes a row address XADD to activate acorresponding word line among the word lines WL1 to WLn. A high sourcevoltage VPP higher than a source voltage VDD may be applied to a gate ofan access transistor of the memory cell 111 during the activation of theword line. The activation of the word line may occur during an enableoperation of the word line.

The bit line sense amplifier array 120 includes bit line senseamplifiers 121-1 to 121-m arranged in an array, a row, or a column. Eachof the bit line sense amplifiers 121-1 to 121-m senses and amplifiesdata outputted from a corresponding memory cell 111. Any bit line senseamplifier may be connected to a bit line pair including a bit line and acomplementary bit line to sense and amplify the potential of the bitline.

The bit line BL1 may mean the bit line pair, and the bit line pair maybe implemented as a folded bit line sense amplifier type, or an open bitline sense amplifier type. However, embodiments of the inventive conceptare not limited thereto. In the case of the open bit line senseamplifier type, another memory cell array separated from the memory cellarray 110 of FIG. 3 may be disposed to face the memory cell array 110 ofFIG. 3 with respect to the bit line sense amplifier. Each of the bitline sense amplifiers 121-1 to 121-m may be a cross-coupled differentialsense amplifier implemented as a P-type sense amplifier and an N-typesense amplifier.

The bit line sense amplifiers 121-1 to 121-m, which are circuit elementsoperating normally during the operation of the semiconductor memorydevice, are distinguished from dummy sense amplifiers implemented in anarea other than the area where the bit line sense amplifier array 120 isimplemented.

The column decoder 130 may decode a column address YADD to generatecolumn select signals CSL1 to CSLm.

In an embodiment, column select transistors in the input/output gate 140transfer the potentials (e.g., voltages) outputted from the bit linesense amplifiers 121-1 to 121-m to local sense amplifiers in the localsense amplifier 160 in response to the column select signals CSL1 toCSLm.

In other words, a column select transistor pair is connected to the bitline pair, and drives the potential outputted from the correspondingsense amplifier and transfers it to the input terminal pair of thecorresponding local sense amplifier 160.

The bit line sense amplifier array 120, the input/output gate 140, andthe local sense amplifier 160 may form a sense amplifier S/A for thememory cell array 110.

The control logic circuit 150 may receive a command, an address, andwrite data from the processor or the memory controller 200. The controllogic circuit 150 may generate various control signals (XADD, YADD,LANG, LAPG, EQ, and the like) required for an access operation, e.g., awrite operation or a read operation, for the memory cell array 110 inresponse to the command and the address.

FIG. 4 shows an example of data output paths of the bit line senseamplifier 120 and the local sense amplifier 160 of FIG. 3 .

Referring to FIG. 4 , a local sense amplifier 160-1 amplifies thepotential difference received from a local input/output line pair LIOand LIOB and outputs it to a global input/output line pair GIO and GIOB.The global input/output line pair GIO and GIOB is connected to aninput/output buffer that buffers data input/output, so that the localsense amplifier 160-1 may provide data stored in the memory cell to theinput/output buffer through the global input/output line pair GIO andGIOB.

The bit line pair connected to the bit sense amplifier 121-1 isconnected to the local input/output line pair LIO and LIOB through acolumn select transistor pair. A first column select transistor 142forming a transistor of the column select transistor pair electricallyconnects the bit line BL to the local input/output line LIO. A secondcolumn select transistor 143 forming a transistor of the column selecttransistor pair electrically connects the complementary bit line BLB tothe complementary local input/output line LIOB.

FIG. 5 shows an example of the arrangement structure of the senseamplifier according to an exemplary embodiment of the presentdisclosure.

Referring to FIG. 5 , the bit line sense amplifier includes an N-typesense amplifier 121 a and a P-type sense amplifier 121 b. The first andsecond column select transistors 142 and 143 may be N-type MOStransistors, and may be driven by a column select signal CSL.

Although not specifically shown, the semiconductor memory device 100 mayinclude a pre-charge and equalization unit (e.g., a circuit) forpre-charging the bit line pair between the first memory cell 111 and theN-type sense amplifier 121 a and between a second memory cell 112 andthe P-type sense amplifier 121 b to a pre-charge voltage and equalizingthe bit line pair to the same potential.

In the bit line structure of FIG. 5 , when the first memory cell 111 isaccessed, the second memory cell 112 is not accessed. In the sensingoperation of the bit line sense amplifier, when the potential of the bitline BL is high, the potential of the complementary bit line BLB is low.On the other hand, in the sensing operation of the bit line senseamplifier, when the potential of the bit line BL is low, the potentialof the complementary bit line BLB is high.

FIG. 6 is an exemplary circuit diagram illustrating a sense amplifier ofFIG. 5 according to an exemplary embodiment.

Referring to FIGS. 4 to 6 , the sense amplifier S/A includes the N-typesense amplifier 121 a, the P-type sense amplifier 121 b, an input/outputgate 140_a, and the local sense amplifier 160.

In an embodiment, the N-type sense amplifier 121 a includes a firsttransistor Tr1 and a second transistor Tr2. The first transistor Tr1 andthe second transistor Tr2 may be connected in series between the bitline BL and the complementary bit line BLB by conductive lines 123 a.For example, the first transistor Tr1 and the second transistor Tr2 maybe N-type transistors. In an embodiment, the source of the firsttransistor Tr1 and the source of the second transistor Tr2 areelectrically connected to the bit line BL and the complementary bit lineBLB, respectively. A first amplification voltage LAB is inputted to thedrain of the first transistor Tr1 and the drain of the second transistorTr2 in response to an N-type sense amplifier driving signal LANG. Forexample, a ground voltage Vss may be used as the first amplificationvoltage LAB. Gates 122 a of the first transistor Tr1 and the secondtransistor Tr2 are electrically connected to the complementary bit lineBLB and the bit line BL by the conductive lines 123 a, respectively. TheN-type sense amplifier 121 a may provide the first amplification voltageLAB to the bit line BL or the complementary bit line BLB depending onvoltage changes of the bit line BL or the complementary bit line BLB.

In an embodiment, the P-type sense amplifier 121 b includes a thirdtransistor Tr3 and a fourth transistor Tr4. The third transistor Tr3 andthe fourth transistor Tr4 may be connected in series between the bitline BL and the complementary bit line BLB by conductive lines 123 b.For example, the third transistor Tr3 and the fourth transistor Tr4 maybe P-type transistors. In an embodiment, the source of the thirdtransistor Tr3 and the source of the fourth transistor Tr4 areelectrically connected to the bit line BL and the complementary bit lineBLB, respectively. A second amplification voltage LA is inputted to thedrain of the third transistor Tr3 and the drain of the fourth transistorTr4 in response to a P-type sense amplifier driving signal LAPG. Forexample, a source voltage Vpp may be used as the second amplificationvoltage LA. In an embodiment, the ground voltage Vss is less than thesource voltage Vpp. Gates 122 b of the third transistor Tr3 and thefourth transistor Tr4 are electrically connected to the complementarybit line BLB and the bit line BL, respectively. The P-type senseamplifier 121 b may provide the second amplification voltage LA to thebit line BL or the complementary bit line BLB depending on voltagechanges of the bit line BL or the complementary bit line BLB.

In an embodiment, the input/output gate 140_a includes a first columnselect transistor 142 and a second column select transistor 143. Thedrain of the first column select transistor 142 and the drain of thesecond column select transistor 143 are electrically connected to thebit line BL and the complementary bit line BLB, respectively. The sourceof the first column select transistor 142 is electrically connected tothe local input/output line LIO, and the source of the second columnselect transistor 143 is electrically connected to the complementarylocal input/output line LIOB. The column select signal CSL is inputtedto the gate of the first column select transistor 142 and the gate ofthe second column select transistor 143.

In an embodiment, the local sense amplifier 160 includes a first NMOStransistor 161 a, a second NMOS transistor 161 b, a third NMOStransistor 164 a and a fourth NMOS transistor 164 b. Although NMOStransistors are illustrated in the present disclosure, this is anexample and the local sense amplifier 160 is not limited to using acertain type of transistor.

The first NMOS transistor 161 a, the second NMOS transistor 161 b, thethird NMOS transistor 164 a, and the fourth NMOS transistor 164 b may beelectrically connected in the local sense amplifier 160 by a conductiveline 163.

A local enable signal PLSAE is provided to a gate 162 a of the firstNMOS transistor 161 a and a gate 162 b of the second NMOS transistor 161b. The local sense amplifier 160 may be activated by the local enablesignal PLSAE.

When the local sense amplifier 160 is activated by the local enablesignal PLSAE, the third NMOS transistor 164 a and the fourth NMOStransistor 164 b may invert and output data of the local input/outputline pair GIO and GIOB to the global input/output line pair LIO andLIOB, respectively.

The semiconductor memory device 100 may operate as follows. First, whenword lines WLi and WLj are activated, switching transistors AT of thememory cells 111 and 112 are turned on and charges move between the bitline BL or the complementary bit line BLB and storage capacitors SC.Then, the N-type sense amplifier 121 a or the P-type sense amplifier 121b amplify the potential difference between the bit line BL and thecomplementary bit line BLB. Then, when the column select signal CSLreaches a first level, the input/output gate 140_a outputs data of thebit line BL or the complementary bit line BLB through the localinput/output line LIO or the complementary local input/output line LIOB.

The local sense amplifier 160 may invert output data of the localinput/output line pair LIO and LIOB and output the inverted data to theglobal input/output line pair GIO and GIOB based on the local enablesignal PLSAE, respectively.

Although not shown, a pre-charge and equalization unit may be present toequalize voltages of the bit line BL and the complementary bit line BLBto the pre-charge voltage before and after the operation of the senseamplifier S/A.

FIG. 7 is a layout diagram illustrating a sense amplifier according toan exemplary embodiment of the present disclosure. FIG. 8 is a diagramfor explaining a cross section taken along line A-A′ of FIG. 7 . FIG. 9is a diagram for explaining a cross section taken along line B-B′ ofFIG. 7 . FIG. 10 is a diagram for explaining a cross section taken alongline C-C′ of FIG. 7 .

Referring to FIGS. 7 to 9 , the sense amplifier S/A includes, on asubstrate 101, a plurality of first active regions ACT1, a plurality ofsecond active regions ACT2, and a third active region ACT3, an adjacentactive region ACTa, a plurality of first gate patterns GP1, a secondgate pattern GP2, a first conductive line CL1, a second conductive lineCL2, a first contact DC1, and a second contact DC2. In embodiment, eachof the first conductive line CL1, a second conductive line CL2, a firstcontact DC1, and a second contact DC2 includes a conductive material.

In an embodiment, the plurality of first active regions ACT1 is arrangedin a row in a second direction Y, and the plurality of second activeregions ACT2 are arranged in a row in the second direction Y. In anembodiment, the plurality of first active regions ACT1 and the pluralityof second active regions ACT2 are spaced apart from each other in afirst direction X.

The first transistor Tr1 or the second transistor Tr2 shown in FIG. 6may be formed in the plurality of first active regions ACT1, and maycorrespond to each of the plurality of first active regions ACT1. Thethird transistor Tr3 or the fourth transistor Tr4 shown in FIG. 6 may beformed in the plurality of second active regions ACT2, and maycorrespond to each of the plurality of second active regions ACT2.Therefore, the components of the bit line sense amplifier array 120 ofFIG. 3 may be disposed in the plurality of first active regions ACT1 andthe plurality of second active regions ACT2.

The third active region ACT3 may be disposed in a space IS where theplurality of first active regions ACT1 and the plurality of secondactive regions ACT2 are spaced apart from each other in the firstdirection X. One or more of the first NMOS transistor 161 a, the secondNMOS transistor 161 b, the third NMOS transistor 164 a, and the fourthNMOS transistor 164 b shown in FIG. 6 may be formed in the third activeregion ACT3. Therefore, the components of the local sense amplifier 160of FIG. 3 may be disposed in the third active region ACT3.

The plurality of first gate patterns GP1 may include a first-first gatepattern GP1_1 and a first-second gate pattern GP1_2. In an embodiment,the first-first gate pattern GP1_1 and the first-second gate patternGP1_2 extend in the first direction X on the third active region ACT3while being spaced apart from each other in the second direction Y. Theplurality of first gate patterns GP1 may contain polysilicon or metal,but embodiments of the first gate patterns GP1 are not limited thereto.

A first gate oxide film GOx1 may be disposed between the plurality offirst gate patterns GP1 and the third active region ACT3. The pluralityof first gate patterns GP1 and the first gate oxide film GOx1 may formone gate structure. In an embodiment, the first gate oxide film GOx1contacts surfaces of the first gate patterns GP1.

In an embodiment, the second gate pattern GP2 extends in the seconddirection Y. In an embodiment, the second gate pattern GP2 is notdisposed on the third active region ACT3 and does not overlap the thirdactive region ACT3. The second gate pattern GP2 may connect theplurality of first gate patterns GP1 to form one multi-finger gatepattern. In other words, the second gate pattern GP2 connects thefirst-first gate pattern GP1_1 and the first-second gate pattern GP1_2.With such an arrangement of the second gate pattern GP2 and theplurality of first gate patterns GP1 may operate as the same gatepattern, and the plurality of first gate patterns GP1 and the secondgate pattern GP2 may correspond to one of the gate 162 a of the firstNMOS transistor 161 a and the gate 162 b of the second NMOS transistor161 b shown in FIG. 6 .

The first conductive line CL1 includes a first-first conductive lineCL1_1 and a first-second conductive line CL1_2. The first-firstconductive line CL1_1 and the first-second conductive line CL1_2 arespaced apart from each other in the second direction Y while extendingin the first direction X on the third active region ACT3. Thefirst-first conductive line CL1_1 and the first-second conductive lineCL1_2 are disposed between the plurality of first gate patterns GP1without overlapping each other in a plan view.

In an embodiment, the first conductive line CL1 includes a firstconductive region CL1_a and a second conductive region CL1_b. The firstconductive region CL1_a may extend in the first direction X on the thirdactive region ACT3, and may include regions of the first-firstconductive line CL1_1 and the first-second conductive line CL1_2 thatare disposed on the third active region ACT3.

In an embodiment, the second conductive region CL1_b is not disposed onthe third active region ACT3 and does not overlap the third activeregion ACT3. In an embodiment, the second conductive region CL1_boverlaps the second gate pattern GP2 in a plan view and is electricallyconnected to the second gate pattern GP2 through the second contact DC2.In an embodiment, the second gate pattern GP2 and the substrate 101 arespaced apart from each other in a third direction Z. Although not shown,an interlayer insulating layer may be disposed between the second gatepattern GP2 and the substrate 101 to electrically insulate them.

The first conductive line CL1 may correspond to the conductive line 163in the local sense amplifier 160 of FIG. 6 . The first conductive lineCL1 may electrically connect the components in the local sense amplifier160 of FIG. 6 , so that the local sense amplifier 160 may operate.

The second conductive line CL2 may extend across the plurality of firstand second active regions ACT1 and ACT2 and the third active region ACT3in the first direction X. Although at least a part of the secondconductive line CL2 may overlap the plurality of first gate patterns GP1in a plan view, the second conductive line CL2 may be disposed above theplurality of first gate patterns GP1 to be separated therefrom.

The second conductive line CL2 according to an embodiment overlaps gatestructures GPa and GOxa disposed on the plurality of first activeregions ACT1 and gate structures GPb and GOxb disposed on the pluralityof second active regions ACT2 in a plan view, and may be electricallyconnected to the gate structures GPb and GOxb through contacts DCa andDCb. Therefore, the transistors disposed on the plurality of firstactive regions ACT1 and the transistors disposed on the plurality ofsecond active regions ACT2 may be electrically connected by the secondconductive line CL2. The second conductive line CL2 may correspond tothe conductive lines 123 a and 123 b in the N-type sense amplifier 121 aand the P-type sense amplifier 121 b of FIG. 6 .

In an exemplary embodiment, the second conductive line CL2 and the firstconductive line CL1 are formed on a same plane without overlapping eachother.

The first contact DC1 includes a first-first contact DC1_1 and afirst-second contact DC1_2. In an embodiment, the first-first contactDC1_1 and the first-second contact DC1_2 extend in the first direction Xon the third active region ACT3 without overlapping each other, and arespaced apart from each other in the second direction Y.

In an embodiment, the first contact DC1 overlaps the first conductiveline CL1 in a plan view. In an embodiment, the first-first contact DC1_1is in contact with and electrically connected to the first-firstconductive line CL1_1 and the third active region ACT3. The region inthe third active region ACT3 that is in contact with the first-firstcontact DC1_1 may correspond to a source/drain region. Similarly, thefirst-second contact DC1_2 may be in contact with and electricallyconnected to the first-second conductive line CL1_2 and the third activeregion ACT3. The region in the third active region ACT3 that is incontact with the first-second contact DC1_2 may correspond to thesource/drain region.

Therefore, the second contact DC2, the first plurality of first gatepatterns GP1, the second gate pattern GP2, and the third active regionACT3 may form one of the gate 162 a of the first NMOS transistor 161 aand the gate 162 b of the second NMOS transistor 161 b in the localsense amplifier 160 of FIG. 6 .

In an embodiment, the first contact DC1 has a long side DC1_a and ashort side DC1_b extending in the first direction X in a plan view. Thelong side DC1_a has a first width W1, and the short side DC1_b has asecond width W2. In an embodiment, the first width W1 is greater thanthe second width W2.

Although not shown, the interlayer insulating layer may be disposedbetween the components that are illustrated or described to be separatedfrom each other in FIGS. 7 to 10 to electrically insulate them.

The adjacent active region ACTa may be disposed in the space IS wherethe plurality of first active regions ACT1 and the plurality of secondactive regions ACT2 are spaced apart from each other in the firstdirection X. The adjacent active region ACTa and the third active regionACT3 may be arranged in the second direction Y.

The adjacent active region ACTa may correspond to the third activeregion ACT3, and the arrangement relationship between the third activeregion ACT3 and the plurality of first gate patterns GP1, the secondgate pattern GP2, the first conductive line CL1, the second conductiveline CL2, the first contact DC1, and the second contact DC2 may beapplied to the adjacent active region ACTa.

Therefore, the second contact DC2, the plurality of first gate patternsGP1, the second gate pattern GP2, and the adjacent active region ACTamay form the gate structure included in the transistors in the columndecoder 130, the input/output (I/O) gate 140, the control logic circuit150, and the local sense amplifier 160 shown in FIG. 3 adjacent to thebit line sense amplifier 120.

In other words, one of the transistors for driving the column decoder130, the input/output (I/O) gate 140, the control logic circuit 150, andthe local sense amplifier 160 shown in FIG. 3 may be formed in theadjacent active region ACTa.

FIG. 11 is a layout diagram illustrating a sense amplifier according toan exemplary embodiment of the present disclosure.

Hereinafter, a sense amplifier according to an embodiment of the presentdisclosure will be described with reference to FIG. 11 . The descriptionwill focus mainly on differences from the sense amplifiers shown inFIGS. 7 to 10 .

Unlike the sense amplifier shown in FIGS. 7 to 10 , in the senseamplifier shown in FIG. 11 , the second gate pattern GP2 includes asecond-first gate pattern GP2_1 and a second-second gate pattern GP2_2that are separated from each other without overlapping in a plan view,and the second contact DC2 includes a second-first contact DC2_1 and asecond-second contact DC2_2 respectively corresponding to thesecond-first gate pattern GP2_1 and the second-second gate patternGP2_2.

In an embodiment, the second-first gate pattern GP2_1 is connected tothe first-first gate pattern GP1_1 to form one gate structure, and thesecond-second gate pattern GP2_2 is connected to the first-second gatepattern GP1_2 to form one gate structure. The second-first gate patternGP2_1 and the first-first gate pattern GP1_1 form one multi-finger gatepattern, and the second-second gate pattern GP2_2 and the first-secondgate pattern GP1_2 form one single finger gate pattern.

The second-first contact DC2_1 electrically connects the second-firstgate pattern GP2_1 to the second conductive region CL1_b, and thesecond-second contact DC2_2 electrically connects the second-second gatepattern GP2_2 to the second conductive region CL1_b.

Therefore, gate voltages may be independently applied to thesecond-first gate pattern GP2_1 and the second-second gate patternGP2_2. However, depending on embodiments, the first-first gate patternGP1_1 and the first-second gate pattern GP1_2 are disposed in the samethird active region ACT3, so that the same gate voltage may be appliedthrough the second-first contact DC2_1 and the second-second contactDC2_2.

FIG. 12 is a layout diagram illustrating a sense amplifier according toan exemplary embodiment of the present disclosure.

Hereinafter, a sense amplifier according to an exemplary embodiment ofthe present disclosure will be described with reference to FIG. 12 . Thedifferences between the sense amplifier shown in FIGS. 7 to 10 and thesense amplifier shown in FIG. 11 will be mainly described.

Compared to the sense amplifier of FIGS. 7 to 10 , the sense amplifierof FIG. 11 further includes a fourth active region ACT4.

The third active region ACT3 may correspond to the third active regionACT3 of FIG. 7 , and the fourth active region ACT4 may correspond to thethird active region ACT3 of FIG. 11 .

The second-first gate pattern GP2_1 extends in the second direction Y.In an embodiment, the second-first gate pattern GP2_1 is not disposed onthe third and fourth active regions ACT3 and ACT4 and does not overlapthe third and fourth active regions ACT3 and ACT4. The second-first gatepattern GP2_1 may form one multi-finger gate pattern by connecting theplurality of first gate patterns GP1 disposed on the third active regionACT3.

The second-second gate pattern GP2_2 is not disposed on the third andfourth active regions ACT3 and ACT4 and does not overlap the third andfourth active regions ACT3 and ACT4. The second-second gate patternGP2_2 may be connected to the first gate pattern GP1 disposed on thethird active region ACT4 to form one single finger gate pattern.

The second-first contact DC2_1 electrically connects the second-firstgate pattern GP2_1 to the second conductive region CL1_b, and thesecond-second contact DC2_2 electrically connects the second-second gatepattern GP2_2 to the second conductive region CL1_b.

Gate voltages may be independently applied to the second-first gatepattern GP2_1 and the second-second gate pattern GP2_2. The third andfourth active regions ACT3 and ACT4 may operate as separate transistors.

FIG. 13 is a diagram for explaining the effect of a sense amplifieraccording to an embodiment of the present disclosure.

Referring to FIGS. 7 and 13 , in the active region included in the localsense amplifier 160, the first gate pattern GP1 and the secondconductive line CL2 extend in the first direction X and overlap eachother in a plan view. Therefore, the area where the first contacts DC1are disposed in the active region may be increased.

The first contact DC1 may have a long side DC1_a extending in the firstdirection X in a plan view.

Therefore, when the first gate pattern GP1 and the second conductiveline CL2 extend in parallel (horizontally), the width of the first gatepattern GP1 in the third active region ACT3, which is determined by theshort side Wb of the third active region ACT3, may be relatively smallerthan that when the first gate pattern GP1 and the second conductive lineCL2 intersect vertically. Since, however, the area of the first contactDC in the active region is increased, the potential difference dGIO ofthe global input/output line pair GIO may be 170 mV at a first time t1during the operation of the semiconductor memory device 100.

When the first gate pattern GP1 and the second conductive line CL2intersect vertically, the width of the first gate pattern GP1 in thethird active region ACT3, which is determined by the long side Wa of thethird active region ACT3, may be relatively greater than that when thefirst gate pattern GP1 and the second conductive line CL2 extend inparallel (horizontally). Since, however, the area of the first contactDC1 in the active region is reduced, the potential difference dGIO ofthe global input/output line pair GIO becomes 163 mV at the first timet1 during the operation of the semiconductor memory device 100.

When the contact area is increased by the parallel (horizontal)arrangement of the first gate pattern GP1 and the second conductive lineCL2 in an embodiment of the present disclosure, the amount of currentmoving through the contact increases. Accordingly, characteristics ofthe transistor are improved, and the data sensing margin of the globalinput/output line may be increased. Further, the potential difference ofthe global input/output line quickly reaches a constant value, so thatthe timing of the read operation may be advanced.

In some instances, features, characteristics, and/or elements describedin connection with a particular embodiment may be used singly or incombination with features, characteristics, and/or elements described inconnection with other embodiments unless otherwise specificallyindicated. Accordingly, it will be understood by those of skill in theart that various changes in form and details may be made in theembodiments without departing from the spirit and scope of the presentinvention.

What is claimed is:
 1. A sense amplifier comprising: a bit line senseamplifier comprising a first transistor and a second transistor spacedapart from each other in a first direction; a second conductive lineconfigured to electrically connect the first transistor to the secondtransistor and extending in the first direction; and a local senseamplifier configured to at least partially overlap the second conductiveline and disposed between the first transistor and the secondtransistor, wherein the local sense amplifier comprises: an activeregion; a plurality of gate patterns at least partially extending in thefirst direction and disposed on the active region; a first contactdisposed between the plurality of gate patterns and comprising a longside extending in the first direction and a short side extending in asecond direction crossing the first direction; and a first conductiveline electrically connected to the first contact while overlapping thefirst contact in a plan view and comprising a first conductive regionextending in the first direction, wherein the long side has a firstwidth in the first direction, the short side has a second width in thesecond direction, and the first width is longer than the second width.2. The sense amplifier of claim 1, wherein the first contact comprises afirst-first contact and a first-second contact that do not overlap eachother, and the first conductive line comprises a first-first conductiveline at least partially overlapping the first-first contact and afirst-second conductive line at least partially overlapping thefirst-second contact.
 3. The sense amplifier of claim 1, wherein thefirst contact and the plurality of gate patterns form one local senseamplifier transistor.
 4. The sense amplifier of claim 1, wherein atleast a part of the second conductive line overlaps the plurality ofgate patterns in a plan view.
 5. The sense amplifier of claim 4, whereinthe second conductive line is separated from the plurality of gatepatterns.
 6. The sense amplifier of claim 1, wherein the firstconductive line and the second conductive line are located on a sameplane without overlapping each other.
 7. The sense amplifier of claim 1,wherein the plurality of gate patterns comprise: a first gate patternextending in the first direction while being disposed on the activeregion and comprising a first-first gate pattern and a first-second gatepattern without overlapping each other in a plan view; and a second gatepattern extending in the second direction without being disposed on theactive region.
 8. The sense amplifier of claim 7, further comprising asecond contact electrically connected to the first-first gate patternand the first-second gate pattern while overlapping the second gatepattern in a plan view.
 9. The sense amplifier of claim 7, wherein theplurality of gate patterns are connected through the second gate patternto form one multi-finger gate pattern.
 10. The sense amplifier of claim7, wherein the second gate pattern comprises a second-first gate patternand a second-second gate pattern separated from each other withoutoverlapping each other, the second-first gate pattern is electricallyconnected to the first-first gate pattern, and the second-second gatepattern is electrically connected to the first-second gate pattern. 11.A semiconductor memory device comprising: a memory cell array comprisinga plurality of memory cells; a bit line sense amplifier comprising afirst transistor and a second transistor configured to sense a potentialdifference between a bit line and a complementary bit line during asensing operation for the plurality of memory cells; an active regioncrossed by a second conductive line electrically connecting the firsttransistor to the second transistor, the active region being separatedfrom a first active of the first transistor and a second active of thesecond transistor; a gate pattern at least partially overlapping thesecond conductive line in a plan view and extending in a first directionin which the second conductive line extends; a first conductive lineextending in the first direction without at least partially overlappingthe gate pattern and the second conductive line; and a first contactelectrically connected to the first conductive line and overlapping thefirst conductive line in a plan view and comprising a long sideextending in the first direction and a short side extending in a seconddirection crossing the first direction, wherein the long side has afirst width in the first direction, the short side has a second width inthe second direction, and the first width is longer than the secondwidth.
 12. The semiconductor memory device of claim 11, wherein the gatepattern comprises a first gate pattern and a second gate pattern spacedapart in the second direction without overlapping each other, and thefirst contact is disposed between the first gate pattern and the secondgate pattern.
 13. The semiconductor memory device of claim 12, whereinthe first contact, the first gate pattern, and the second gate patternform one local sense amplifier transistor.
 14. The semiconductor memorydevice of claim 11, wherein the first conductive line and the secondconductive line are located on a same plane without overlapping eachother.
 15. A semiconductor memory device comprising: a memory cell arraycomprising a plurality of memory cells configured to store data; a bitline sense amplifier comprising a first transistor and a secondtransistor configured to sense a potential difference between a firstpotential of a bit line and a second potential of a complementary bitline during a sensing operation for the plurality of memory cells; alocal sense amplifier configured to receive the first potential and thesecond potential from the bit line sense amplifier and provide data to aglobal input/output line, the local sense amplifier being disposedbetween the first transistor and the second transistor, wherein thelocal sense amplifier comprises: an active region; a plurality of gatepatterns disposed on the active region so as to at least partiallyoverlap a second conductive line electrically connecting the firsttransistor to the second transistor; a first contact disposed betweenthe plurality of gate patterns and comprising a long side extending in afirst direction in which the second conductive line extends and a shortside extending in a second direction crossing the first direction; and afirst conductive line electrically connected to the first contact whileoverlapping the first contact in a plan view and comprising a firstconductive region extending in the first direction, wherein the longside has a first width in the first direction, the short side has asecond width in the second direction, and the first width is longer thanthe second width.
 16. The semiconductor memory device of claim 15,further comprising: a first column select transistor configured totransfer the first potential to the local sense amplifier in response toa column select signal; and a second column select gate configured totransfer the second potential to the local sense amplifier in responseto the column select signal.
 17. The semiconductor memory device ofclaim 15, wherein the second conductive line is separated from theplurality of gate patterns.